Flash memory is non-volatile computer memory that can be electrically erased and reprogrammed. It is a technology that has typically been used in memory cards, and USB flash drives (thumb drives, handy drive), which are used for general storage and transfer of data between computers and other Digital products. Flash memory costs far less than EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, solid-state storage is needed. Examples of applications include laptop computers, digital audio players, digital cameras and mobile phones. It has also gained popularity in the game console market, where it is often used instead of EEPROMs or battery-powered static RAM (SRAM) for game save data.
Embedded flash technology consists of flash memory built directly onto a processor. For example, a graphics chip may have embedded memory instead of using separate memory chips. With the continuing growth of consumer and mobile electronics markets, chip makers are racing to make ever smaller features, which increasingly require more advanced embedded flash technologies as they begin to include more functionality.
In addition to consumer and mobile electronics markets, the use of embedded flash technology is also becoming more prevalent in high density applications that require low power such as microcontroller cores, high-speed ASICs (application-specific integrated circuits) and multimedia ICs (integrated circuits).
The production of embedded flash chips is not without difficulty. For example, due to the high topography of the typical flash cell structure, however, it is a challenge to perform word line etching without damaging the individual flash cells. To avoid such damage, word line polysilicon planarization may be performed using a chemical-mechanical polishing (CMP). A problem with using such CMP process is that an 800 Angstrom step height (see FIG. 2) may still exist after poly-CMP. This step height can cause an abnormal SiON thickness (see FIG. 3) that will induce an abnormal polysilicon profile during subsequent poly etching. An abnormal polysilicon profile can result in undesirable variations in etched channel length as well as reduced control over etched channel depth.
Thus, it would be desirable to provide a planarization process that eliminates undesirable step heights associated with prior techniques, thereby minimizing or eliminating subsequent abnormal SiON thicknesses that can induce abnormal polysilicon profiles.